8 PWM
- Código:
#include "TM4C123.h" // Device header
// configure the system to get its clock from the PLL
#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
unsigned long H,L;
unsigned long T = 16777216;
void SysTick_Handler(void){
if(GPIOF->DATA & 0x04){ // toggle
GPIOF->DATA &= ~0x04; // make PF low
SysTick->LOAD = L-1; // reload value for low phase
} else{
GPIOF->DATA |= 0x04; // make PA5 high
SysTick->LOAD = H-1; // reload value for high phase
}
}
__asm void
Delay(unsigned long n)
{
SUBS R0, #1
BNE Delay
bx LR ;//the link register is providing the address to branch to.
}
void SysTick_Interrupt_Init(){
SysTick->CTRL = 0; // Disable the SysTick during configuration
SysTick->VAL = 0;
SysTick->CTRL = (0x1<<2)|(0x1<<1)|(0x1<<0); // 111 Select the clock system and enable the SysTick
}
void PLL_Init(void){
// 0) Use RCC2
SYSCTL_RCC2_R |= 0x80000000; // USERCC2
// 1) bypass PLL while initializing
SYSCTL_RCC2_R |= 0x00000800; // BYPASS2, PLL bypass
// 2) select the crystal value and oscillator source
SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0) // clear XTAL field, bits 10-6
+ 0x00000540; // 10101, configure for 16 MHz crystal
SYSCTL_RCC2_R &= ~0x00000070; // configure for main oscillator source 10001111
// 3) activate PLL by clearing PWRDN
SYSCTL_RCC2_R &= ~0x00002000;
// 4) set the desired system divider
SYSCTL_RCC2_R |= 0x40000000; // use 400 MHz PLL, DIV400
SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000) // clear system clock divider
+ (4<<22); // configure for 80 MHz clock, 400/(4+1) = 80MHz
// 5) wait for the PLL to lock by polling PLLLRIS
while((SYSCTL_RIS_R & 0x00000040)==0){}; // wait for PLLRIS bit
// 6) enable use of PLL by clearing BYPASS
SYSCTL_RCC2_R &= ~0x00000800;
}
void PWM(unsigned short Duty_Cycle){
H = 1677722*Duty_Cycle - 1;
L = T-H;
GPIOF->DATA |= 0x04;
SysTick->LOAD = H-1; //Load the number of ticks.
}
int main()
{
int j;
PLL_Init();
SYSCTL->RCGC2|=(0x1<<5);// The clock of PORTF
GPIOF->DEN |= 0xFF; //PORTF is Digital enable now
GPIOF->DIR|=(0x1<<2)|(0x1<<3)|(0x1<<1);//LEDs are outputs
GPIOF->DATA &= ~0x04; // make PF low
SysTick_Interrupt_Init(); // reload value for 500us
while(1){
for(j=9;j>0;j--)
{
PWM(j);
Delay(13333333); // delay ~0.5 sec at 80 MHz
}
}
}
// configure the system to get its clock from the PLL
#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
unsigned long H,L;
unsigned long T = 16777216;
void SysTick_Handler(void){
if(GPIOF->DATA & 0x04){ // toggle
GPIOF->DATA &= ~0x04; // make PF low
SysTick->LOAD = L-1; // reload value for low phase
} else{
GPIOF->DATA |= 0x04; // make PA5 high
SysTick->LOAD = H-1; // reload value for high phase
}
}
__asm void
Delay(unsigned long n)
{
SUBS R0, #1
BNE Delay
bx LR ;//the link register is providing the address to branch to.
}
void SysTick_Interrupt_Init(){
SysTick->CTRL = 0; // Disable the SysTick during configuration
SysTick->VAL = 0;
SysTick->CTRL = (0x1<<2)|(0x1<<1)|(0x1<<0); // 111 Select the clock system and enable the SysTick
}
void PLL_Init(void){
// 0) Use RCC2
SYSCTL_RCC2_R |= 0x80000000; // USERCC2
// 1) bypass PLL while initializing
SYSCTL_RCC2_R |= 0x00000800; // BYPASS2, PLL bypass
// 2) select the crystal value and oscillator source
SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0) // clear XTAL field, bits 10-6
+ 0x00000540; // 10101, configure for 16 MHz crystal
SYSCTL_RCC2_R &= ~0x00000070; // configure for main oscillator source 10001111
// 3) activate PLL by clearing PWRDN
SYSCTL_RCC2_R &= ~0x00002000;
// 4) set the desired system divider
SYSCTL_RCC2_R |= 0x40000000; // use 400 MHz PLL, DIV400
SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000) // clear system clock divider
+ (4<<22); // configure for 80 MHz clock, 400/(4+1) = 80MHz
// 5) wait for the PLL to lock by polling PLLLRIS
while((SYSCTL_RIS_R & 0x00000040)==0){}; // wait for PLLRIS bit
// 6) enable use of PLL by clearing BYPASS
SYSCTL_RCC2_R &= ~0x00000800;
}
void PWM(unsigned short Duty_Cycle){
H = 1677722*Duty_Cycle - 1;
L = T-H;
GPIOF->DATA |= 0x04;
SysTick->LOAD = H-1; //Load the number of ticks.
}
int main()
{
int j;
PLL_Init();
SYSCTL->RCGC2|=(0x1<<5);// The clock of PORTF
GPIOF->DEN |= 0xFF; //PORTF is Digital enable now
GPIOF->DIR|=(0x1<<2)|(0x1<<3)|(0x1<<1);//LEDs are outputs
GPIOF->DATA &= ~0x04; // make PF low
SysTick_Interrupt_Init(); // reload value for 500us
while(1){
for(j=9;j>0;j--)
{
PWM(j);
Delay(13333333); // delay ~0.5 sec at 80 MHz
}
}
}
Código PWM para el GPIOB
#include "TM4C123.h" // Device header
// configure the system to get its clock from the PLL
#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
// begins the definition of the registers of Port B to be used as a GPIO
#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
// ends the definition of the registers of Port B
unsigned long H,L;
unsigned long T = 16777216;
void SysTick_Handler(void){
if(GPIOF->DATA & 0x04){ // toggle
GPIOF->DATA &= ~0x04; // make PF low
GPIO_PORTB_DATA_R &= ~0x01;
SysTick->LOAD = L-1; // reload value for low phase
} else{
GPIOF->DATA |= 0x04; // make PA5 high
GPIO_PORTB_DATA_R |= ~0x01;
SysTick->LOAD = H-1; // reload value for high phase
}
}
__asm void
Delay(unsigned long n)
{
SUBS R0, #1
BNE Delay
bx LR ;//the link register is providing the address to branch to.
}
void SysTick_Interrupt_Init(){
SysTick->CTRL = 0; // Disable the SysTick during configuration
SysTick->VAL = 0;
SysTick->CTRL = (0x1<<2)|(0x1<<1)|(0x1<<0); // 111 Select the clock system and enable the SysTick
}
void PortB_Init(void){
volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000002; //1) activate clock for Port B
delay = SYSCTL_RCGC2_R; //allow time for clock to start
GPIO_PORTB_AMSEL_R &= ~0xFF; // 3) disable analog on PA5
GPIO_PORTB_PCTL_R &= ~0xFFFFFFFF; // 4) PCTL GPIO on PA5
GPIO_PORTB_DIR_R |= 0xFF; // 5) direction PortB output
GPIO_PORTB_AFSEL_R &= ~0xFF; // 6) PB regular port function
GPIO_PORTB_DEN_R |= 0xFF; // 7) enable the PB as a digital port
}
void PLL_Init(void){
// 0) Use RCC2
SYSCTL_RCC2_R |= 0x80000000; // USERCC2
// 1) bypass PLL while initializing
SYSCTL_RCC2_R |= 0x00000800; // BYPASS2, PLL bypass
// 2) select the crystal value and oscillator source
SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0) // clear XTAL field, bits 10-6
+ 0x00000540; // 10101, configure for 16 MHz crystal
SYSCTL_RCC2_R &= ~0x00000070; // configure for main oscillator source 10001111
// 3) activate PLL by clearing PWRDN
SYSCTL_RCC2_R &= ~0x00002000;
// 4) set the desired system divider
SYSCTL_RCC2_R |= 0x40000000; // use 400 MHz PLL, DIV400
SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000) // clear system clock divider
+ (4<<22); // configure for 80 MHz clock, 400/(4+1) = 80MHz
// 5) wait for the PLL to lock by polling PLLLRIS
while((SYSCTL_RIS_R & 0x00000040)==0){}; // wait for PLLRIS bit
// 6) enable use of PLL by clearing BYPASS
SYSCTL_RCC2_R &= ~0x00000800;
}
void PWM(unsigned short Duty_Cycle){
H = 1677722*Duty_Cycle - 1;
L = T-H;
GPIOF->DATA |= 0x04;
SysTick->LOAD = H-1; //Load the number of ticks.
}
int main()
{
int j;
PLL_Init();
SYSCTL->RCGC2|=(0x1<<5);// The clock of PORTF
GPIOF->DEN |= 0xFF; //PORTF is Digital enable now
GPIOF->DIR|=(0x1<<2)|(0x1<<3)|(0x1<<1);//LEDs are outputs
GPIOF->DATA &= ~0x04; // make PF low
PortB_Init();
SysTick_Interrupt_Init(); // reload value for 500us
PWM(5);
while(1){
}
}
// configure the system to get its clock from the PLL
#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
// begins the definition of the registers of Port B to be used as a GPIO
#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
// ends the definition of the registers of Port B
unsigned long H,L;
unsigned long T = 16777216;
void SysTick_Handler(void){
if(GPIOF->DATA & 0x04){ // toggle
GPIOF->DATA &= ~0x04; // make PF low
GPIO_PORTB_DATA_R &= ~0x01;
SysTick->LOAD = L-1; // reload value for low phase
} else{
GPIOF->DATA |= 0x04; // make PA5 high
GPIO_PORTB_DATA_R |= ~0x01;
SysTick->LOAD = H-1; // reload value for high phase
}
}
__asm void
Delay(unsigned long n)
{
SUBS R0, #1
BNE Delay
bx LR ;//the link register is providing the address to branch to.
}
void SysTick_Interrupt_Init(){
SysTick->CTRL = 0; // Disable the SysTick during configuration
SysTick->VAL = 0;
SysTick->CTRL = (0x1<<2)|(0x1<<1)|(0x1<<0); // 111 Select the clock system and enable the SysTick
}
void PortB_Init(void){
volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000002; //1) activate clock for Port B
delay = SYSCTL_RCGC2_R; //allow time for clock to start
GPIO_PORTB_AMSEL_R &= ~0xFF; // 3) disable analog on PA5
GPIO_PORTB_PCTL_R &= ~0xFFFFFFFF; // 4) PCTL GPIO on PA5
GPIO_PORTB_DIR_R |= 0xFF; // 5) direction PortB output
GPIO_PORTB_AFSEL_R &= ~0xFF; // 6) PB regular port function
GPIO_PORTB_DEN_R |= 0xFF; // 7) enable the PB as a digital port
}
void PLL_Init(void){
// 0) Use RCC2
SYSCTL_RCC2_R |= 0x80000000; // USERCC2
// 1) bypass PLL while initializing
SYSCTL_RCC2_R |= 0x00000800; // BYPASS2, PLL bypass
// 2) select the crystal value and oscillator source
SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0) // clear XTAL field, bits 10-6
+ 0x00000540; // 10101, configure for 16 MHz crystal
SYSCTL_RCC2_R &= ~0x00000070; // configure for main oscillator source 10001111
// 3) activate PLL by clearing PWRDN
SYSCTL_RCC2_R &= ~0x00002000;
// 4) set the desired system divider
SYSCTL_RCC2_R |= 0x40000000; // use 400 MHz PLL, DIV400
SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000) // clear system clock divider
+ (4<<22); // configure for 80 MHz clock, 400/(4+1) = 80MHz
// 5) wait for the PLL to lock by polling PLLLRIS
while((SYSCTL_RIS_R & 0x00000040)==0){}; // wait for PLLRIS bit
// 6) enable use of PLL by clearing BYPASS
SYSCTL_RCC2_R &= ~0x00000800;
}
void PWM(unsigned short Duty_Cycle){
H = 1677722*Duty_Cycle - 1;
L = T-H;
GPIOF->DATA |= 0x04;
SysTick->LOAD = H-1; //Load the number of ticks.
}
int main()
{
int j;
PLL_Init();
SYSCTL->RCGC2|=(0x1<<5);// The clock of PORTF
GPIOF->DEN |= 0xFF; //PORTF is Digital enable now
GPIOF->DIR|=(0x1<<2)|(0x1<<3)|(0x1<<1);//LEDs are outputs
GPIOF->DATA &= ~0x04; // make PF low
PortB_Init();
SysTick_Interrupt_Init(); // reload value for 500us
PWM(5);
while(1){
}
}