Memoria de Instrucciones de 32 bits en Verilog para procesadores MIPS
Video:
Código:
module rom( adr, WD, clk, WE, dout);
input clk,WE;
input [31:0] adr, WD;
output [31:0] dout;
reg [31:0] mem [63:0];
initial
begin
$readmemh("rom.dat", mem);
end
always @(posedge clk)
begin
if (WE)
mem[adr] <= WD;
$writememh("rom.dat",mem,0,63);
end
assign dout = mem[adr];
endmodule
module rom( adr, WD, clk, WE, dout);
input clk,WE;
input [31:0] adr, WD;
output [31:0] dout;
reg [31:0] mem [63:0];
initial
begin
$readmemh("rom.dat", mem);
end
always @(posedge clk)
begin
if (WE)
mem[adr] <= WD;
$writememh("rom.dat",mem,0,63);
end
assign dout = mem[adr];
endmodule
Testbench:
module rom_tb;
reg clk,WE;
reg [31:0] adr, WD;
wire [31:0] dout;
rom utt( adr, WD, clk, WE, dout);
initial
begin
adr = 32'd0;
WD = 32'd0;
WE = 1'b0;
#40;
adr = 32'd5;
WD = 32'd10;
WE = 1'b1;
#20;
end
always
#10 clk = ~clk;
endmodule
module rom_tb;
reg clk,WE;
reg [31:0] adr, WD;
wire [31:0] dout;
rom utt( adr, WD, clk, WE, dout);
initial
begin
adr = 32'd0;
WD = 32'd0;
WE = 1'b0;
#40;
adr = 32'd5;
WD = 32'd10;
WE = 1'b1;
#20;
end
always
#10 clk = ~clk;
endmodule
// Archivo de datos .dat
// Instrucciones Guarda estos datos en un //archivo llamado rom.dat
| rom.dat |